Analog memory cells, such as Flash memory cells, are typically read by comparing the analog cell values to one or more read thresholds. Various techniques for setting and adjusting read thresholds are known in the art. For example, U.S. Pat. No. 5,657,332, whose disclosure is incorporated herein by reference, describes methods for recovering from hard errors in a solid-state memory system. A memory system includes an array of memory cells, each cell capable of having its threshold voltage programmed or erased to an intended level. An error checking scheme is provided for each of a plurality of groups of cells for identifying read errors therein. A read reference level is adjusted before each read operation on the individual group of cells containing read errors, each time the read reference level being displaced a predetermined step from a reference level for normal read, until the error checking means no longer indicates read errors. The drifted threshold voltage of each cell associated with a read error is re-written to its intended level.
U.S. Patent Application Publication 2007/0091677, whose disclosure is incorporated herein by reference, describes techniques for reading data from one or more Flash memory cells, and for recovering from read errors. In some embodiments, in the event of an error correction failure by an error detection and correction module, the Flash memory cells are re-read at least once using one or more modified reference voltages, until successful error correction may be carried out.
U.S. Pat. No. 6,963,505, whose disclosure is incorporated herein by reference, describes methods for determining a reference voltage. In some embodiments, a set of operating reference cells is established to be used in operating cells in a Non-Volatile Memory (NVM) block or array. At least a subset of cells of the NVM block or array may be read using each of two or more sets of test reference cells, where each set of test reference cells may generate or otherwise provide reference voltages at least slightly offset from each other set of test reference cells. For each set of test reference cells used to read at least a subset of the NVM block, a read error rate may be calculated or otherwise determined. A set of test reference cells associated with a relatively low read error rate may be selected as the set of operating reference cells to be used in operating other cells, outside the subset of cells, in the NVM block or array.
U.S. Patent Application Publication 2010/0091535, whose disclosure is incorporated herein by reference, describes various techniques for adjusting read thresholds of analog memory cells. In one of the disclosed techniques, data is encoded with an Error Correction Code (ECC) before it is stored in the memory cells. When retrieving data from the memory cells, the ECC is decoded in order to correct read errors. For a given read error that was corrected by the ECC, the direction of the error, i.e., the programming level with which the read storage value was erroneously associated before applying ECC correction, is determined. Information regarding directions of corrected errors is used for adjusting the read thresholds.